1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) is composed of memory cells each made up of a transistor and a capacitor. The capacitor is composed of a lower electrode, a dielectric film, and an upper electrode. In recent years, with advanced semiconductor miniaturizing techniques, ensuring a required area for electrodes in the DRAM has been difficult.
Thus, to increase the area for the electrodes, Japanese Patent Laid-Open No. 2001-217406 discloses a technique of using an inner wall and an outer wall formed like crowns as an upper electrode and a lower electrode, respectively, to increase capacity. FIG. 11 shows a recessed lower electrode similar to the lower electrode in Japanese Patent Laid-Open No. 2001-217406.
In FIG. 11, the lower electrode is denoted by 105. The lower electrode in FIG. 11 is formed as follows. First, a transistor and a contact plug are formed such that the contact plug is electrically connected to one of a source region and a drain region of the transistor. Thereafter, an interlayer insulating film is formed all over the resulting surface A mask pattern is then formed on a portion of the interlayer insulating film which is located on a region forming a memory cell portion.
Thereafter, by performing wet etching, the interlayer insulating film is removed except for the portion of the interlayer insulating film which is located under the mask pattern, to form an opening. A conductive material is then deposited on an inner wall of the opening to form a tower electrode. The interlayer insulating film is then removed. At this time, the internal surface (the interior of the recessed structure) of the lower electrode is exposed.
Efforts have been made to develop a method of preventing formation of a step between the memory cell portion and the peripheral circuit portion, Japanese Patent Laid-Open No. 2001-217406 and WO 97/019468 disclose methods of reducing a step that may be formed at the boundary between the memory cell portion and the peripheral circuit portion.